Mixed-signal verification, a critical aspect of chip design, encompasses both digital and analog verification. These verification processes occur within module-level and chip-level environments, each with distinct objectives that often complement one another. Digital verification primarily focuses on ensuring the flawless functionality of register read and write operations, as well as […]
Chatgpt: How good is it in SystemVerilog Real Number Modeling?
Chatgpt, the fastest-growing application, has proven to be a nice helping hand for programmers. It can not generate codes that actually compile and are much better than expected from an AI model. While I have been using it to get some help in writing javascript codes, I wanted to check […]
AMS Verification: many different roles under one title
AMS verification roles are becoming more and more important as chips are getting more complex. Plenty of chips have digital and analog functionality so integrated that it Is almost impossible to properly verify them in only a digital environment or analog environment. This leads managers to form AMS verification teams […]
Can analog modeling engineers take the roles of AMS verification engineers?
The answer is Yes and considering how resource-tight these design and verification teams are – it’s the best option to have engineers who can do both modeling and verification. Now, it will vary from team to team. Most big companies have analog design teams, digital design teams, digital verification teams, […]
Limitations of SystemVerilog in analog model development
Mixed signal verification has been evolving for a number of years now. Verification teams in different companies or even different products, do it differently depending on their needs. There are teams that prefer everything in one language whether it is RTL, analog models, or test benches. It is also not […]
Common reasons your Verilog-AMS model simulation is slow
Verilog-AMS models or models in general are developed hoping for a faster simulation. There can be many different reasons for model development, but a fast simulation is usually expected. Even after spending resources and time, sometimes verification engineers find themselves in a situation where the simulation is extremely slow. Slow […]